The present invention relates generally to an integrated circuit (IC) design, and more particularly to a resistor structure for an electrostatic (ESD) protection circuit.
As semiconductor devices continue to shrink in size, their susceptibility to ESD damage is a growing concern for IC designs. An ESD event occurs when, for example, an object containing electric-static charges touches one or more pins of an IC. While the ESD event typically lasts for a very short period of time, the resulting voltage can reach thousands of volts and damage the vulnerable parts of semiconductor devices, such as the gate dielectric layers. In order to protect the semiconductor devices from the ESD damages, one or ESD protection circuits are often implemented at the pins of the IC for dissipating the ESD current as soon as the ESD event occurs. In a normal operation, the ESD protection circuit is turned off so that it does not interfere the functioning of the core circuit that it protects. During the ESD event, the ESD protection circuit is turned on to create a current path for dissipating the ESD current, thereby protecting the devices in the core circuit from damage.
One conventional ESD protection circuit is configured by a grounded-gate NMOS (GGNMOS) transistor coupled with a resistor, which is typically formed by continuous N-type doped region with one end coupled to a supply voltage and another coupled to the GGNMOS transistor. During the ESD event, the resistor passes the ESD current to turn on the GGNMOS transistor, thereby creating a current path for dissipating the ESD current.
Conventionally, an additional resistance protective oxide (RPO) layer is provided on top of the N-type doped region in order to avoid the formation of a silicide layer thereon during its fabrication process. Otherwise, the silicide layer would have directly coupled the GGNMOS transistor to the supply voltage, and caused a direct punch through for its underlying poly-silicon layer.
One drawback of such conventional ESD protection circuit is that the usage of the RPO layer complicates its fabrication process, thereby increasing the costs. Since the process of forming the RPO layer cannot be integrated in the process of constructing the GGNMOS transistor, a mask in addition to the ones for constructing the transistor is therefore required.
Another drawback of the conventional ESD protection circuit is that the resistor occupies a relatively large area in an IC. Conventionally, the N-type doped region of the resistor and the source/drain regions of the GGNMOS transistor are formed simultaneously. The impurity density of the N-type doped region is therefore as high as that of the source/drain regions of the GGNMOS transistor. Due to the high impurity density, the N-type doped region needs to occupy a large area in order to achieve a certain desired resistance.
It is therefore desirable to improve the resistor structure for the ESD protection circuit in order to simplify its fabrication process and reduce its size.